1. Field of the Invention
The present invention is related to a semiconductor memory device, and particularly to circuitry for processing an input signal such as an address signal.
2. Description of the Related Art
FIG. 1 shows a schematic overall arrangement of a conventional semiconductor memory device. The shown memory Device is a dynamic type semiconductor memory device to which row address signals and column address signals are time-division multiplexedly applied.
Referring to FIG. 1, the memory device includes a memory cell array MA having a plurality of memory cells arranged in rows and columns, an address buffer circuit AB receiving externally applied address signal bits Add0-Addm to generate internal address signals Ar and Ac, a row decoder RD receiving and decoding an internal row address signal Ar to generate a row selection signal designating a row in memory array MA, a column decoder CD receiving and decoding an internal column address signal Ac to generate a column selection signal designating a column in memory array MA, and a sense/IO gate block SG including sense amplifiers and IO gates.
Sense amplifiers are provided on the respective columns of memory array MA, and sense and amplify data of memory cells on a selected row. IO gates are provided for the respective columns and connecting to an internal data bus a selected column in response to the column selection signal from column decoder CD. Row decoder RD may include word drivers provided for the rows of memory array MA and for driving a selected row to a selected state according to the row selection signal.
The memory device further includes a data write circuit WB receiving an external write data DI and generating an internal write data to write the internal write data to a selected memory cell on a selected row and a selected column, and a data read circuit RB receiving an internal read data from a selected memory cell to generate an external read data DQ.
A timing control signal generator TG receives a row address strobe signal /RAS providing a timing at which row address signals are latched, a column address strobe signal /CAS providing a timing at which column address signals are latched, and a write enable signal /WE designating data read/write mode of operation, to generate various internal control signals. Now, operations of the memory device of FIG. 1 will be described with reference to a timing chart of FIG. 2.
In FIG. 2, a signal RAS is an internal basic signal to define a memory access cycle and is generated in response to the row address strobe signal /RAS, from the generator TG.
When the signal /RAS goes low at time T21, a memory cycle starts. Address buffer circuit AB incorporates applied address signal bits Add0-Addm as a row address signal to generate an internal row address signal X1 in response to the rising of the signal RAS generated in synchronization with the row address strobe signal /RAS. Row decoder RD is activated in response to the signal RAS to decode the row address signal X1 to select a row of memory cells in the memory cell array MA. Then, sense amplifiers in the block SG is activated to amplify and latch data of the memory cells on the selected row.
At time T22, the signal /CAS goes low, and responsively the address buffer circuit AB incorporates applied address signal bits Add0-Addm as a column address signal Y1 to generate an internal column address signal. Column decoder CD is activated according to the falling of the signal /CAS and decodes the internal column address signal to generate a column selection signal. In the block SG, IO gate provided for a column designated by the column selection signal is rendered conductive. Writing or reading of data to a selected memory cell is effected by data write circuit WB or data read circuit RB. When the signal /WE is at a low level, writing of data is effected. When the signal /WE is at a high level, reading of data is effected.
The signals /RAS and RAS determine the activation timings of circuits related to a row selection operation, and the signal /CAS determines the activation timings of the circuits related to a column selection operation.
Date read timing is determined by the signal /CAS, and data write timing is determined by the signals /CAS and /WE.
In general, an access time TRAS required for the external output of a valid data from the falling of the signal /RAS is determined in the specification. Similarly, an access time TCAS is also determined for the signal /CAS in the specification.
If data of a memory cell on a different row and a different column is required, the signal /RAS is once deactivated at time T23 and the memory device is initialized. At time T24, the signal /RAS goes low, or is activated, and another memory cycle starts. A row address signal X2 and a column address signal Y2 are incorporated sequentially, and a memory cell is selected, and data DQ of the selected memory cell is outputted. When the memory cell data is read out, the signal /RAS goes high, or is deactivated at time T25.
As described above, a memory cycle is determined by the signal BRAS. Address signals are incorporated and then memory cell data is read out. In other words, incorporation of an address signal and reading of data of a corresponding memory cell cannot be performed asynchronously. Such asynchronisity also holds for data writing operation. One memory cycle includes an address incorporation time period and memory access operation period and thus a memory cycle period cannot be reduced.
The object of the present invention is to provide a semiconductor memory device in which incorporation of an address signal and accessing to a corresponding memory cell are performed asynchronously with each other.
A semiconductor memory device according to the present invention includes a memory cell array having a plurality of memory cells arranged in rows and columns, a decoder for selecting a memory cell in the memory cell array in accordance with a received address signal, an address storage for storing a plurality of address signals, and a controller for causing the address storage to store address signals and supplying an address signal from the address storage to the decoder in response to a control signal instructing a start of an internal operation.
While an internal operation is performed, an address signal is incorporated and stored in the address storage. An address signal stored in the address storage are supplied to the decoder in each starting of internal operation. An address incorporation time period is hidden in the internal operation period, and a memory cycle time can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.